1. Field of the Invention
The present patent concerns data communication from a transmitter chip to a receiver chip over multiple high-speed serial lanes.
2. Description of the Related Art
For data communication between two chips, it is common to use parallel buses with a relatively low data rate per I/O pin, whereby the interface circuitry remains simple. In order to obtain higher data rates, the bus width can be increased while keeping the data rate per input-output (I/O) pin constant. However, there exist applications where the required data rate is that high that the number of I/O pins per chip and the number of lines between the two chips are a significant constraint in the design. For example, one such application is an analog-to-digital (A/D) converter operating at a rate of several billion samples per second. At such data rates, it becomes necessary to develop advanced interface circuitry at the transmitter and receiver end in order to transmit data as fast as physically possible over each line. Thus a high number of links between the two chips can be avoided. The data rate per line can be maximized by high-speed serial schemes in which the receiver recovers both clock and data from the signal. Such high-speed serial interfaces are already in widespread use in many telecommunication- and computer-related products. Examples are fiber optic interfaces or hard disks.
One issue that has to be addressed when a serial data transmission scheme is designed is synchronization between transmitter and receiver. Special indicators are inserted in the data flow in order to determine where a data frame begins and ends. In order to take care of this additional signalling effort, the bit transfer rate over the physical channel is somewhat higher than the rate at which useful data is written to the transmitter interface. For instance, the 10 Gb/s Ethernet standard is based on frames with a length of 66 bits where 64 bits constitute payload data and 2 bits are used for synchronization. The transmit clock rate specified in this standard is 10.31 GHz that is 66/64·10 GHz. The ratio between the transmit clock rate and the clock rate of the data to transmit is integer, since the data is received from the transmitter on a 64-bit wide parallel bus that is clocked with a frequency of 156.25 MHz which is typically derived from the same frequency reference as the 10 GHz base clock. The handling of clock frequencies at circuit interfaces or if occurring within circuits which are not a multiple of a common base clock is a substantial difficulty or even poses intractable problems. An example solution could be FIFO buffering implying, however, a large overhead in hardware and power consumption.
For such applications, it is possible to implement transmitter circuits that distribute the data over several high-speed serial lanes.
In telecommunication systems, insertion of synchronization symbols into data streams is a complex process involving several layers. Usually from layer to layer additional information such as address information, check sums, or additional flags for the communication between layers having the same task within the OSI model are attached to the data. The layer most closely related to the invention described herein is the Physical Layer (PHY) which is further decomposed in the 802.3 IEEE Standard for Information Technology and its amended document 802.3ae. It can be roughly described as build up of the elements GMII (Gigabit Media Independent Interface), the Physical Coding Sublayer (PCS), the Physical Medium Attachment (PMA), and a Medium Dependent Interface (MDI).
An encoder that is used in this standard and that was published in A. Widmer, P. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”, IBM Journal of Research and Development, Vol. 27, No. 5, pp. 440-451, September 1983 expands incoming parallel data by means of a look-up table. This expanded data is serialized and then transmitted over a serial data line. This encoder is considered an alternative possibility to insert additional data such as headers into a parallel and constantly incoming data stream in a controlled way. As is described later, in contrast to the present invention no buffer is required since the solution is based on a look-up table.